//#pragma once
//#include <cstdint>
//
//#ifndef ARD_FUNCTION_ARM
//#define ARD_FUNCTION_ARM
//
//enum class BranchType {
//	BranchType_DIRCALL, // Direct Branch with link
//	BranchType_INDCALL, // Indirect Branch with link
//	BranchType_ERET, // Exception return (indirect)
//	BranchType_DBGEXIT, // Exit from Debug state
//	BranchType_RET, // Indirect branch with function return hint
//	BranchType_DIR, // Direct branch
//	BranchType_INDIR, // Indirect branch
//	BranchType_EXCEPTION, // Exception entry
//	BranchType_TMFAIL, // Transaction failure
//	BranchType_RESET, // Reset
//	BranchType_UNKNOWN
//}; // Other
//
//enum class WFxType { WFxType_WFE, WFxType_WFI, WFxType_WFET, WFxType_WFIT };
//
//enum class MemOp { MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH };
//
//enum class SecurityState {
//	SS_NonSecure,
//	SS_Root,
//	SS_Realm,
//	SS_Secure
//};
//
//enum class AccessType {
//	AccessType_IFETCH, // Instruction FETCH
//	AccessType_GPR, // Software load/store to a General Purpose Register
//	AccessType_ASIMD, // Software ASIMD extension load/store instructions
//	AccessType_SVE, // Software SVE load/store instructions
//	AccessType_SME, // Software SME load/store instructions
//	AccessType_IC, // Sysop IC
//	AccessType_DC, // Sysop DC (not DC {Z,G,GZ}VA)
//	AccessType_DCZero, // Sysop DC {Z,G,GZ}VA
//	AccessType_AT, // Sysop AT
//	AccessType_NV2, // NV2 memory redirected access
//	AccessType_SPE, // Statistical Profiling buffer access
//	AccessType_GCS, // Guarded Control Stack access
//	AccessType_TRBE, // Trace Buffer access
//	AccessType_GPTW, // Granule Protection Table Walk
//	AccessType_TTW // Translation Table Walk
//};
//
//enum class MemAtomicOp {
//	MemAtomicOp_GCSSS1,
//	MemAtomicOp_ADD,
//	MemAtomicOp_BIC,
//	MemAtomicOp_EOR,
//	MemAtomicOp_ORR,
//	MemAtomicOp_SMAX,
//	MemAtomicOp_SMIN,
//	MemAtomicOp_UMAX,
//	MemAtomicOp_UMIN,
//	MemAtomicOp_SWP,
//	MemAtomicOp_CAS
//};
//
//enum class CacheOp {
//	CacheOp_Clean,
//	CacheOp_Invalidate,
//	CacheOp_CleanInvalidate
//};
//
//enum class CacheOpScope {
//	CacheOpScope_SetWay,
//	CacheOpScope_PoU,
//	CacheOpScope_PoC,
//	CacheOpScope_PoE,
//	CacheOpScope_PoP,
//	CacheOpScope_PoDP,
//	CacheOpScope_PoPA,
//	CacheOpScope_ALLU,
//	CacheOpScope_ALLUIS
//};
//
//enum class CacheType {
//	CacheType_Data,
//	CacheType_Tag,
//	CacheType_Data_Tag,
//	CacheType_Instruction
//};
//
//enum class VARange {
//	VARange_LOWER,
//	VARange_UPPER
//};
//
//enum class PARTIDspaceType {
//	PIdSpace_Secure,
//	PIdSpace_Root,
//	PIdSpace_Realm,
//	PIdSpace_NonSecure
//};
//
//enum class Regime {
//	Regime_EL3, // EL3
//	Regime_EL30, // EL3&0 (PL1&0 when EL3 is AArch32)
//	Regime_EL2, // EL2
//	Regime_EL20, // EL2&0
//	Regime_EL10 // EL1&0
//};
//
//enum class M32Mode {
//	M32_User = 0b10000,
//	M32_FIQ = 0b10001,
//	M32_IRQ = 0b10010,
//	M32_Svc = 0b10011,
//	M32_Monitor = 0b10110,
//	M32_Abort = 0b10111,
//	M32_Hyp = 0b11010,
//	M32_Undef = 0b11011,
//	M32_System = 0b11111
//};
//
//enum class PASpace {
//	PAS_NonSecure,
//	PAS_Secure,
//	PAS_Root,
//	PAS_Realm
//};
//
//enum class MemType { MemType_Normal, MemType_Device };
//
//enum class MemTagType {
//	MemTag_Untagged,
//	MemTag_AllocationTagged,
//	MemTag_CanonicallyTagged
//};
//
//enum class DeviceType { DeviceType_GRE, DeviceType_nGRE, DeviceType_nGnRE, DeviceType_nGnRnE };
//
//enum class Shareability {
//	Shareability_NSH,
//	Shareability_ISH,
//	Shareability_OSH
//};
//
//enum class  ErrorState {
//	ErrorState_UC, // Uncontainable
//	ErrorState_UEU, // Unrecoverable state
//	ErrorState_UEO, // Restartable state
//	ErrorState_UER, // Recoverable state
//	ErrorState_CE, // Corrected
//	ErrorState_Uncategorized,
//	ErrorState_IMPDEF
//};
//
//enum class Fault {
//	Fault_None,
//	Fault_AccessFlag,
//	Fault_Alignment,
//	Fault_Background,
//	Fault_Domain,
//	Fault_Permission,
//	Fault_Translation,
//	Fault_AddressSize,
//	Fault_SyncExternal,
//	Fault_SyncExternalOnWalk,
//	Fault_SyncParity,
//	Fault_SyncParityOnWalk,
//	Fault_GPCFOnWalk,
//	Fault_GPCFOnOutput,
//	Fault_AsyncParity,
//	Fault_AsyncExternal,
//	Fault_TagCheck,
//	Fault_Debug,
//	Fault_TLBConflict,
//	Fault_BranchTarget,
//	Fault_HWUpdateAccessFlag,
//	Fault_Lockdown,
//	Fault_Exclusive,
//	Fault_ICacheMaint
//};
//
//enum class GPCF {
//	GPCF_None, // No fault
//	GPCF_AddressSize, // GPT address size fault
//	GPCF_Walk, // GPT walk fault
//	GPCF_EABT, // Synchronous External abort on GPT fetch
//	GPCF_Fail // Granule protection fault
//};
//
//enum class TGx {
//	TGx_4KB,
//	TGx_16KB,
//	TGx_64KB
//};
//typedef struct 
//{
//	PARTIDspaceType mpam_sp;
//	uint16_t partid;
//	uint8_t pmg;
//}MPAMinfo;
//
//typedef struct
//{
//	GPCF gpf;
//	int32_t level;
//}GPCFRecord;
//
//typedef struct
//{
//	PASpace paspace;
//	uint64_t address;//56bit
//}FullAddress;
//
//typedef struct
//{
//	AccessType acctype;
//	uint32_t el : 2; // Acting EL for the access
//	SecurityState ss; // Acting Security State for the access
//	bool acqsc; // Acquire with Sequential Consistency
//	bool acqpc; // FEAT_LRCPC: Acquire with Processor Consistency
//	bool relsc; // Release with Sequential Consistency
//	bool limitedordered; // FEAT_LOR: Acquire/Release with limited ordering
//	bool exclusive; // Access has Exclusive semantics
//	bool atomicop; // FEAT_LSE: Atomic read-modify-write access
//	MemAtomicOp modop; // FEAT_LSE: The modification operation in the 'atomicop' access
//	bool nontemporal; // Hints the access is non-temporal
//	bool read; // Read from memory or only require read permissions
//	bool write; // Write to memory or only require write permissions
//	CacheOp cacheop; // DC/IC: Cache operation
//	CacheOpScope opscope; // DC/IC: Scope of cache operation
//	CacheType cachetype; // DC/IC: Type of target cache
//	bool pan; // FEAT_PAN: The access is subject to PSTATE.PAN
//	bool transactional; // FEAT_TME: Access is part of a transaction
//	bool nonfault; // SVE: Non-faulting load
//	bool firstfault; // SVE: First-fault load
//	bool first; // SVE: First-fault load for the first active element
//	bool contiguous; // SVE: Contiguous load/store not gather load/scatter store
//	bool streamingsve; // SME: Access made by PE while in streaming SVE mode
//	bool ls64; // FEAT_LS64: Accesses by accelerator support loads/stores
//	bool mops; // FEAT_MOPS: Memory operation (CPY/SET) accesses
//	bool rcw; // FEAT_THE: Read-Check-Write access
//	bool rcws; // FEAT_THE: Read-Check-Write Software access
//	bool toplevel; // FEAT_THE: Translation table walk access for TTB address
//	VARange varange; // FEAT_THE: The corresponding TTBR supplying the TTB
//	bool a32lsmd; // A32 Load/Store Multiple Data access
//	bool tagchecked; // FEAT_MTE2: Access is tag checked
//	bool tagaccess; // FEAT_MTE: Access targets the tag bits
//	bool ispair; // Access represents a Load/Store pair access
//	bool highestaddressfirst; // FEAT_LRCPC3: Highest address is accessed first
//	MPAMinfo mpam; // FEAT_MPAM: MPAM information
//}AccessDescriptor;
//
//typedef struct
//{
//	Fault statuscode; // Fault Status
//	AccessDescriptor accessdesc; // Details of the faulting access
//	FullAddress ipaddress; // Intermediate physical address
//	GPCFRecord gpcf; // Granule Protection Check Fault record
//	FullAddress paddress; // Physical address
//	bool gpcfs2walk; // GPC for a stage 2 translation table walk
//	bool s2fs1walk; // Is on a Stage 1 translation table walk
//	bool write; // TRUE for a write, FALSE for a read
//	bool s1tagnotdata; // TRUE for a fault due to tag not accessible at stage 1.
//	bool tagaccess; // TRUE for a fault due to NoTagAccess permission.
//	int32_t level; // For translation, access flag and Permission faults
//	bool extflag; //bit IMPLEMENTATION DEFINED syndrome for External aborts
//	bool secondstage; // Is a Stage 2 abort
//	bool assuredonly; // Stage 2 Permission fault due to AssuredOnly attribute
//	bool toplevel; // Stage 2 Permission fault due to TopLevel
//	bool overlay; // Fault due to overlay permissions
//	bool dirtybit; // Fault due to dirty state
//	uint8_t domain; //bits(4) Domain number, AArch32 only
//	ErrorState merrorstate; // Incoming error state from memory
//	bool maybe_false_match; // Watchpoint matches rounded range
//	int32_t watchpt_num; // Matching watchpoint number
//	uint8_t debugmoe; //bits(4) Debug method of entry, from AArch32 only
//}FaultRecord;
//
//typedef struct
//{
//	uint8_t attrs; //bits(2) See MemAttr_*, Cacheability attributes
//	uint8_t hints; //bits(2) See MemHint_*, Allocation hints
//	bool transient;
//}MemAttrHints;
//
//typedef struct
//{
//	MemType memtype;
//	DeviceType device; // For Device memory types
//	MemAttrHints inner; // Inner hints and attributes
//	MemAttrHints outer; // Outer hints and attributes
//	Shareability shareability; // Shareability attribute
//	MemTagType tags; // MTE tag type for this memory.
//	bool notagaccess; // Allocation Tag access permission
//	bool  xs;//bit XS attribute 
//}MemoryAttributes;
//
//typedef struct
//{
//	FaultRecord fault; // fault.statuscode indicates whether the address is valid
//	MemoryAttributes memattrs;
//	FullAddress paddress;
//	bool s1assured; // Stage 1 Assured Translation Property
//	bool s2fs1mro; // Stage 2 MRO permission for Satge 1
//	uint16_t mecid; // FEAT_MEC: Memory Encryption Context ID
//	uint64_t vaddress;
//}AddressDescriptor;
//
//typedef struct
//{
//	// A64-VMSA exclusive parameters
//	uint8_t ha : 1; // TCR_ELx.HA
//	uint8_t hd : 1; // TCR_ELx.HD
//	uint8_t tbi : 1; // TCR_ELx.TBI{x}
//	uint8_t tbid : 1; // TCR_ELx.TBID{x}
//	uint8_t nfd : 1; // TCR_EL1.NFDx or TCR_EL2.NFDx when HCR_EL2.E2H == '1'
//	uint8_t e0pd : 1; // TCR_EL1.E0PDx or TCR_EL2.E0PDx when HCR_EL2.E2H == '1'
//	uint8_t d128 : 1; // TCR_ELx.D128
//	uint8_t aie : 1; // (TCR2_ELx/TCR_EL3).AIE
//	uint8_t mair2; // MAIR2_ELx
//	uint8_t ds : 1; // TCR_ELx.DS
//	uint8_t ps : 3; // TCR_ELx.{I}PS
//	uint8_t txsz : 6; // TCR_ELx.TxSZ
//	uint8_t epan : 1; // SCTLR_EL1.EPAN or SCTLR_EL2.EPAN when HCR_EL2.E2H == '1'
//	uint8_t dct : 1; // HCR_EL2.DCT
//	uint8_t nv1 : 1; // HCR_EL2.NV1
//	uint8_t cmow : 1; // SCTLR_EL1.CMOW or SCTLR_EL2.CMOW when HCR_EL2.E2H == '1'
//	uint8_t pnch : 1; // TCR{2}_ELx.PnCH
//	uint8_t disch : 1; // TCR{2}_ELx.DisCH
//	uint8_t haft : 1; // TCR{2}_ELx.HAFT
//	uint8_t mtx : 1; // TCR_ELx.MTX{y}
//	uint8_t skl : 2; // TCR_ELx.SKL
//	uint8_t pie : 1; // TCR2_ELx.PIE or TCR_EL3.PIE
//	uint8_t pir; //S1PIRType PIR_ELx
//	uint8_t pire0; //S1PIRType PIRE0_EL1 or PIRE0_EL2 when HCR_EL2.E2H == '1'
//	uint8_t emec : 1; // SCTLR2_EL2.EMEC or SCTLR2_EL3.EMEC
//	uint8_t amec : 1; // TCR2_EL2.AMEC0 or TCR2_EL2.AMEC1 when HCR_EL2.E2H == '1'
//	uint8_t fng : 1;
//	// A32-VMSA exclusive parameters
//	uint8_t t0sz : 3; // TTBCR.T0SZ
//	uint8_t t1sz : 3; // TTBCR.T1SZ
//	uint8_t uwxn; // SCTLR.UWXN
//	// Parameters common to both A64-VMSA & A32-VMSA (A64/A32)
//	TGx tgx; // TCR_ELx.TGx / Always TGx_4KB
//	uint8_t irgn : 2; // TCR_ELx.IRGNx / TTBCR.IRGNx or HTCR.IRGN0
//	uint8_t orgn : 2; // TCR_ELx.ORGNx / TTBCR.ORGNx or HTCR.ORGN0
//	uint8_t sh : 2; // TCR_ELx.SHx / TTBCR.SHx or HTCR.SH0
//	uint8_t hpd : 1; // TCR_ELx.HPD{x} / TTBCR2.HPDx or HTCR.HPD
//	uint8_t ee : 1; // SCTLR_ELx.EE / SCTLR.EE or HSCTLR.EE
//	uint8_t wxn : 1; // SCTLR_ELx.WXN / SCTLR.WXN or HSCTLR.WXN
//	uint8_t ntlsmd : 1; // SCTLR_ELx.nTLSMD / SCTLR.nTLSMD or HSCTLR.nTLSMD
//	uint8_t dc : 1; // HCR_EL2.DC / HCR.DC
//	uint8_t sif : 1; // SCR_EL3.SIF / SCR.SIF
//	MAIR_EL1 mair; //MAIRType  MAIR_ELx / MAIR1:MAIR0 or HMAIR1:HMAIR0
//}S1TTWParams;
//
//typedef struct
//{
//	Fault statuscode; // Fault Status
//	bool extflag; //bit IMPLEMENTATION DEFINED syndrome for External aborts
//	ErrorState merrorstate; // Optional error state returned on a physical memory access
//	uint64_t store64bstatus; //bits(64) Status of 64B store
//}PhysMemRetStatus;
//
//extern bool SPESampleInFlight;
//#endif // !ARD_FUNCTION_ARM
